There is an increasing need for more integrated and function-rich electronic devices. To meet such a need, various forms of packaging and integration techniques have been developed and used, from printed circuit board (PCB) populated with semiconductor chips to System-on-a-Chip (SoC) and System-in-Package (SiP) devices.
Generally the design flow of an electronic device involves verification of signal timings. Timing verification tools are supposed to provide accurate delay estimation so as to evaluate the delay of signals propagating through a circuit network. This requirement applies also to the highly integrated and sophisticated electronic devices mentioned above.
An electronic circuit system may be designed either on a single platform, as in the case of SoC, or on multiple platforms. Different methods are used to verify the system depending on this difference. More specifically, the qualification of “on a single platform” refers to, for example, the case where circuit blocks used in the electronic device in question were designed by the same vendor. Another case is where such circuit blocks will be fabricated by using the same manufacturing process. Yet another case is where such circuit blocks were designed on a uniform development environment (e.g., calculating signal delays with the same set of formulas, extracting library parameters under the same conditions, and using the same computer-aided design (CAD) tools).
The general outlines of the above-noted two types of timing verification methods will be described below, beginning with an example of a uni-platform system. FIG. 15 illustrates a structure of an SoC. The illustrated semiconductor device, or SoC, 500 includes two circuit modules M1 and M2. These circuit modules M1 and M2 were designed on a single platform, hence uni-platform modules. Specifically, the first circuit module M1 is formed from four buffers 111 to 114 and one latch circuit FF1. An input data signal given to data input terminal IN1 of the semiconductor device 500 is routed to the first circuit module M1 and propagates through its input terminal A1, buffer 111, latch circuit FF1, buffer 112, and output terminal X1 in that order before it is sent out to the second circuit module M2. A clock signal given to clock input terminal CK of the semiconductor device 500 is routed to the first circuit module M1 and propagates through its clock input terminal CK1, buffers 113 and 114, and clock output terminal CK01 in that order before it is sent out to the second circuit module M2. The latch circuit FF1 operates with a clock signal supplied via the buffer 113.
Similar to the first circuit module M1 described above, the second circuit module M2 is formed from four buffers 121 to 124 and one latch circuit FF2. The output data signal of the first circuit module M1 is routed to the second circuit module M2 and propagates through input terminal A2, buffer 121, latch circuit FF2, and buffer 122, and output terminal X2 in that order before it is sent out from an output terminal OUT1 of the semiconductor device 500. The clock output signal of the first circuit module M1 is routed to the second circuit module M2 and propagates through its clock input terminal CK2, buffers 123 and 124, and clock output terminal CKO2 before it is sent out from a clock output terminal CKO of the semiconductor device 500. The latch circuit FF2 operates with a clock signal supplied from via the buffer 123.
To verify such a system of uni-platform circuit modules or blocks, the timing verification process collects delay data for each of the data and clock paths in the entire system and subjects the collected data to a circuit simulator or a static timing analysis (STA) tool. In the present case, the unified specifications of libraries corresponding to those circuit blocks make it possible to calculate system-level signal delays straight away from design data values extracted from the libraries.
FIG. 16 illustrates an example of library specifications used for delay verification. Specifically, FIG. 16 depicts a buffer 140 formed from two complementary metal-oxide semiconductor (CMOS) inverters as an example of a circuit block provided in a library used in delay verification. As can be seen in FIG. 16, typical library parameters include terminal-to-terminal delays Tpd and slew rates. Slew rate parameters include input slew rate Tsin corresponding to the input end of a circuit block, and output slew rate Tsout corresponding to the output end of the same.
The terminal-to-terminal delay Tpd of a circuit block denotes the amount of propagation delay between an input and its corresponding output of that block. More specifically, this parameter Tpd is defined based on the time points at which the input signal VIN and output signal VOUT cross a predetermined threshold. The threshold may be defined as a percentage of voltage level to the maximum amplitude of signals (e.g., 50% in the example of FIG. 16).
The slew rate represents the rate of change of a signal at its rising edge or falling edge, which is expressed as, for example, the time between the start and end points of that change. The actual signals may, however, exhibit a slow change at the beginning of their transitions. They may also have an overshoot and undershoot at the end of their rising and falling transitions, respectively. For these reasons, the definition of slew rates disregards both the beginning and ending portions of transitions, but focuses on the central portion where the signal keeps changing in a relatively linear fashion. Referring to the example of FIG. 16, the thresholds designating the start point and end point of a rising transition are set to 20% and 80%, respectively, of the maximum amplitude.
Signal delays produced in a circuit actually involve several factors. One is known as the gate delay, which refers to the inherent delay of a circuit. Another is a slew rate dependent delay, which refers to the variation of terminal-to-terminal delay Tpd due to changes of input signal slew rate Tsin. Yet another factor is a load capacitance dependent delay, which refers to the variation of output slew rate Tsout due to changes of output load capacitance CL under the condition of a fixed input slew rate Tsin. Unlike the latter two delay factors, the gate delay has no dependency on the slew rate or load capacitance.
FIGS. 17A and 17B illustrate an example of what the library provides in table form. Referring to FIG. 17A, the library provides a Tpd table representing the slew rate dependent signal delay noted above, as a collection of terminal-to-terminal delay values Tpd at various points of output load capacitance CL and input signal slew rate Tsin. Referring to FIG. 17B, the library also provides a Tsout table representing the load capacitance dependent delay noted above, as a collection of output slew rate values Tsout at various points of output load capacitance CL and input signal slew rate Tsin. The library stores those sets of delay data for each type of cells used in circuit blocks.
Signal delays in an electronic device may be calculated with various ways, depending on the vender, process, and design tool used. For example, one ordinary calculation method begins with defining constraints for input buffers according to the slew rate of signals supplied from an external source. Other constraints are wire capacitance (capacitance of wires to succeeding circuits or cells) and pin capacitance. The ordinary method determines output slew rate values Tsout by applying those constraints when it looks up the Tsout table discussed above.
The method handles internal circuits (cells) of a semiconductor chip in a similar way. That is, the method assigns parameters of a preceding circuit to a succeeding circuit as part of its constraints. For example, the output slew rate of the preceding circuit will be included in the constraints, together with the wire and pin capacitance associated with the succeeding circuit. For output buffers, the method defines their constraints from, for example, the output slew rate of preceding circuits. Also determined as a constraint is output load capacitance of those output buffers. More specifically, the output load capacitance of a buffer can be calculated from, among others, the input capacitance of its succeeding circuit block, which is described in the library of that circuit block. When the constraints are defined, the terminal-to-terminal delay Tpd of each cell in the system can then be obtained by looking up the above-described Tpd table with those constraint values.
FIG. 18 illustrates a structure of a PCB as an example of a system formed from circuit blocks designed on different platforms. An example of a timing verification method for this system will now be described below, with reference to this FIG. 18 and subsequent drawings.
Mounted on the PCB 600 of FIG. 18 are two semiconductor chips CP1 and CP2 from different vendors. Those semiconductor chips CP1 and CP2 have the same circuit structure as what have been discussed as circuit modules M1 and M2 in FIG. 15. Accordingly, FIG. 18 uses the same reference numerals and symbols as FIG. 5 for the corresponding components.
Conventionally the timing verification of an electronic device containing such multi-vendor circuit blocks is performed in two stages. The first stage verifies each semiconductor chip one by one, and the second stage verifies the interface portions connecting those semiconductor chips with each other.
FIG. 19 illustrates the first stage of timing verification which evaluates each individual semiconductor chip used in a PCB. Signal delays and timings in a chip are verified through circuit simulation or static timing analysis (STA) with a set of external constraints for the chip, including input signal specifications and output load conditions. Referring to, for example, the first semiconductor chip CP1 illustrated in the left half of FIG. 19, the verification process for this chip starts with determining the input signal slew rates Tsin and skews for use as the chip's input constraints, taking into consideration the conditions of external signals supplied from off-board sources (step S21). The process then determines the output load capacitance of the first semiconductor chip CP1 as output constraints, taking into consideration the input pin capacitance of the succeeding chip CP2 and associated wiring capacitance (step S22). Those two steps S21 and S22 permit calculation of the terminal-to-terminal delay Tpd of each cell in the first semiconductor chip CP1.
The verification process then defines input constraints of the second semiconductor chip CP2 (step S23). Specifically, the output slew rates Tsout of the first semiconductor chip CP1 are used as part of input constraints of the second semiconductor chip CP2. Other input constraints include skews and other parameters related to the signals supplied from the first semiconductor chip CP1 to the second semiconductor chip CP2. Those parameters come from the results of, for example, a static timing analysis which has been performed on the first semiconductor chip CP1. The verification process then determines output constraints of the second semiconductor chip CP2 (step S24) including the output load capacitance of each signal that goes out of the board, based on the wire capacitance and other parameters associated with those outgoing signals. Steps S23 and S24 permit calculation of the terminal-to-terminal delay Tpd of each cell, in the second semiconductor chip CP2. In this way, the first stage of the verification process calculates signal delays and performs circuit simulation and STA for each individual circuit block contained in the board.
FIG. 20 illustrates chip-to-chip timing verification in a PCB development process. This is what has been mentioned as the second stage of verification process, which uses a board simulator to verify the timing design by using the input and output signal paths of each circuit block and their associated transmission line models. For illustrative purposes, FIG. 20 focuses on the output buffers 115 and 116 of the first semiconductor chip CP1 and the input buffers 125 and 126 of the second semiconductor chip CP2. This portion of the PCB 600 is subjected to the board simulator so as to verify the timing of propagating signals. The verification process uses the information on slew rates and skews in the first semiconductor chip CP1 to define a set of input constraints for the second semiconductor chip CP2 (step S31). The verification process observes the output of each input buffer 125 and 126 to determine whether those output signals change their states as expected (step S32).
The above-described two-stage verification process intends to ensure the system-level timing design of an electronic device containing multiple circuit blocks designed on different platforms. However, the circuit simulation and STA performed during this process does not actually test the designed system as a whole.
As another technique related to the above-described timing verification process, Japanese Laid-open Patent Publication No. 7-65041 (1995) proposes an adaptive method of evaluating signal delays. Considering the fact that design data may be given as a mixture of components at different design levels, the proposed method changes the way of calculating delays depending on the design level of each section of design data, according to some other data defining which circuit sections to evaluate (see, for example, paragraphs Nos. 0017 to 0027 and FIG. 5 of the noted publication). The proposed method, however, does not assume that the design data may include components developed on different vendor platforms.
As yet another related technique, Japanese Laid-open Patent Publication No. 2000-286342 proposes a layout design method for a large-scale integrated (LSI) circuit using intellectual property (IP) cores. This method places appropriate buffers between IP cores so as to satisfy their timing requirements. By so doing, the proposed method makes it possible to pursue the timing design of circuits outside the IP cores independently of the internal timing design of the IP cores (see, for example, paragraph Nos. 0025 to 0032 and FIG. 1 of the noted publication).
The timing design of an electronic device is verified through a system-level circuit simulation or STA using signal delay data calculated for all constituent circuit blocks. This approach is, however, not possible in some type of devices like the foregoing PCB 600 because their constituent circuit blocks are based on different platforms. That is, the difference of their development platforms introduces an error in the results of delay calculation. More specifically, this error derives from the fact that different platforms use different definitions of terminal-to-terminal delays, as well as determining slew rates with different thresholds.
FIG. 21 illustrates delay data errors that could be introduced when evaluating signals propagating from one circuit block to another. Specifically, FIG. 21 gives a simplified example of delay data errors associated with a signal propagating between the first and second semiconductor chips CP1 and CP2 discussed in FIG. 18. For the first semiconductor chip CP1, its terminal-to-terminal delay Tpd is defined at 50% of full amplitude, and its slew rate is defined to be the time for a signal to change from 20% to 80% of its full amplitude. For the second semiconductor chip CP2, on the other hand, its terminal-to-terminal delay Tpd is defined at 60% of full amplitude, and its slew rate is defined to be the time for a signal to change from 10% to 90% of its full amplitude.
Referring to FIG. 21, the first semiconductor chip CP1 contains an output buffer 115 with a terminal-to-terminal delay of Tpd_11 measured with the 50% threshold. On the other hand, the second semiconductor chip CP2 contains an input buffer 125 with a terminal-to-terminal delay of Tpd_12 measured with the 60% threshold. The total delay of those circuits in the semiconductor chips CP1 and CP2 is calculated by adding up their respective delays Tpd_11 and Tpd_12. The result contains, however, an error Tpd_err due to the different threshold definitions of CP1 and CP2. That is, the true delay time is greater than the sum of Tpd_11 and Tpd_12 by this error Tpd_error, as in the case illustrated in FIG. 21. The same error Tpd_err may act the other way around in some other cases. That is, in the case of falling edge, the sum of Tpd_11 and Tpd_12 includes this Tpd_err two times.
Similarly, a difference in the slew rate threshold would produce an error Ts_err in slew rate calculation. Think of, for example, the output slew rate Tsout of the first semiconductor chip CP1. If this Tsout is used as a constraint on the input buffer 125 of the second semiconductor chip CP2, the calculated delay time value may fall short by Ts_err or may include this Ts_err two times, depending on the edge. Accordingly, the user cannot obtain correct verification results.